Workshop on IC Advances in China (ICAC) 2024

March 19-22, 2024

Shanghai, China

Welcome to Workshop on IC Advances in China (ICAC) 2024

华人芯片设计技术研讨会 2024

The goal of the ICAC Workshop is to build a platform for the academia and industry people in China to have more open technical discussions, and to generate possible collaborations, and to brainstorm new ideas and directions. Therefore, we are gathering the top Chinese IC design scholars/engineers who published ISSCC and/or JSSC in the past two years, and try to attract more attendees from the IC industry.

We hope the workshop speakers and audiences produce chemical reactions, as well as electrical resonances as our logo shows. To this end, language should not be a problem. This workshop uses both Chinese and English. This workshop does not publish papers, and the oral speakers are by invitation only.


In Alphabetical Order of Last Name...

Chi-Hang Chan, University of Macau

Yong Chen, University of Macau

Zhiyuan Chen, Fudan University

Lin Cheng, University of Science and Technology of China

Wei Deng, Tsinghua University

Chunmeng Dou, The Institute of Microelectronics (IME) of the Chinese Academy of Sciences (CAS)

Yuan Du, Nanjing University

Chao Fan, Xi'an Jiaotong University

Guangyin Feng, South China University Of Technology

Hao Gao, Southeast University

Yuan Gao, Southern University of Science and Technology

Jianping Guo, Sun Yat-sen University

Mingqiang Guo, University of Macau

Yanshu Guo, Tsinghua University

Yuekang Guo, Shanghai Jiao Tong University

Wei Hong, Southeast University (Keynote)

Zhiliang Hong, Fudan University

Sanming Hu, Southeast University

Mo Huang, University of Macau

Haikun Jia, Tsinghua University

Wening Jiang, Fudan University

Yang Jiang, University of Macau

Junmin Jiang, Southern University of Science and Technology

Hailong Jiao, Peking University

Lu Jie, Tsinghua University

Chi-Seng Lam, University of Macau

Man-Kay Law, University of Macau

Ka-Meng Lei, University of Macau

Hongge Li, Beihang University

Lianming Li, Southeast University

Wei Li, Fudan University

Xianbo Li, Sun Yat-sen University

Xueqing Li, Tsinghua University

Leibo Liu, Tsinghua University

Liyuan Liu, Institute of Semiconductors, CAS

Maliang Liu, Xidian University

Ming Liu, Fudan University (Keynote)

Xun Liu, The Chinese University of Hong Kong,Shenzhen

Yongpan Liu, Tsinghua University

Yan Lu, University of Macau

Guansheng Lv, Tsinghua University

Yufei Ma, Peking University

Pui In Mak, University of Macau

Fangyu Mao, Light Semibucks (Wuxi) Company Limited

Xiangyu Mao, University of Macau

Miao Meng, Tongji University

Xin Ming, University of Electronic Science and Technology of China

Dongfang Pan, University of Science and Technology of China

Quan Pan, Southern University of Science and Technology

Sining Pan, Tsinghua University

Huizhen Qian, Xidian University

Weiwei Shan, Southeast University

Linxiao Shen, Peking University

Xin Si, Southeast University

Shuang Song, Zhejiang University

Houjun Sun, Beijing Institute of Technology

Nan Sun, Tsinghua University

Kai Tang, Hunan University

Xiyuan Tang, Peking University

Zhong Tang, Vango Technologies, Inc.

Fengbin Tu, The Hong Kong University of Science and Technology

Chi-Wa U, University of Macau

Cheng Wang, University of Electronic Science and Technology of China

Yang Wang, Tsinghua University

Yong Wang, University of Electronic Science and Technology of China

Yuan Wang, Peking University

Yuanfei Wang, University of Macau

Zheng Wang, University of Electronic Science and Technology of China

Liang Wu, The Chinese University of Hong Kong

Jiawei Xu, Fudan University

Hao Xu, Fudan University

Wei Xu, Shenzhen University

Quan Xue, South China University of Technology

Le Ye, Peking University

Jun Yin, University of Macau

Yun Yin, Fudan University

Shouyi Yin, Tsinghua University

Wei-Han Yu, University of Macau

Yiming Yu, University of Electronic Science and Technology of China

Chenchang Zhan, Southern University of Science and Technology

Chuan Zhang, Southeast University

Feng Zhang, The Institute of Microelectronics (IME) of the Chinese Academy of Sciences (CAS)

Lei Zhang, Tsinghua University

Minglei Zhang, University of Macau

Bo Zhao, Zhejiang University

Jian Zhao, Shanghai Jiao Tong University

Bo Zhou, Beijing Institute of Technology

Jun Zhou, University of Electronic Science and Technology of China

Shenglong Zhuo, Tongji University

To be updated...


Mar. 20, 2024

Multimodal Analog Front-End Circuits for Wearable Healthcare

Simultaneous recordings of multiple physiological signals in a wearable form factor enables more easy and comprehensive assessment of one’s health condition. However, detecting low-amplitude, low-frequency physiological signals from multiple aggressors like noise, motion artifacts, and environmental interferences remains the great challenge in practice. This talk presents several recent examples of biopotential, bioimpedance and optical interface circuits, with focus on analog circuits techniques to optimize noise, input impedance, input dynamic range, and power consumption for wearable scenarios.

徐佳伟,复旦大学 Jiawei Xu received the M.Sc. and Ph.D. degrees in the Delft University of Technology, The Netherlands. From 2006 to 2018, he was with imec/Holst Centre, Eindhoven. In 2018, he joined Fudan University, Shanghai, China, as a faculty member. His research group works on integrated circuits for wearable and implantable medical devices, precision sensor interfaces, and battery power management. He is a TPC member of ISSCC and CICC, an Associate Editor for IEEE Transactions on VLSI Systems.

Reconfigurable Machine Learning Processor: Fundamental Concepts, Applications, and Future Trends

A reconfigurable ML processor increases hardware flexibility to accommodate various ML algorithms and speeds up processing time while consuming less power. Typically, a reconfigurable ML processor includes multiple reconfiguration hierarchies, such as chip-level, processing element array-level, and processing element-level reconfigurations. Chip-level reconfiguration dynamically adjusts the parallelism of multi-chip systems to minimize computation latency and data access. Processing element array-level reconfiguration changes the dataflow or mapping of the computing engine to fully reuse the on-chip data, reducing the memory access. Processing element-level reconfiguration changes the function of the computing unit, such as computing precision and sparsity processing pattern, to increase the bit-wise hardware utilization. This tutorial explores the fundamental concepts of reconfigurable technology, discusses its applications in both digital and analog ML processors, and prospects for future development trends in reconfigurable technology.

尹首一,清华大学 Shouyi Yin received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tsinghua University, Beijing, China, in 2000, 2002, and 2005, respectively. He has worked with Imperial College, London, U.K., as a Research Associate. He is currently a full professor and the vice director of School of Integrated Circuits in Tsinghua University. His research interests include reconfigurable computing, AI processors and high level synthesis. He has published more than 100 journal papers and more than 50 conference papers. He has served as technical program committee member in the top VLSI and EDA conferences such as A-SSCC, MICRO, DAC, ICCAD and ASPDAC. He is the associate editor of IEEE TCAS-I, ACM TRETS and Integration, the VLSI journal.

Silicon-based Millimeter Wave Integrated Circuit Design Technology

This tutorial mainly focused on the design technology of silicon-based millimeter-wave integrated circuits, which including the characteristics of commonly used passive components in silicon-based millimeter-wave integrated circuits (such as transmission lines, transformers), the design process of silicon-based millimeter-wave integrated circuits, the design methods of core circuit modules (such as low-noise amplifiers, power amplifiers, voltage-controlled oscillators), and considerations for system-level link design. This tutorial integrated the research progress of the research group, aiming to help the audience to understand the basic design methods and the latest developments in the field of silicon-based millimeter-wave integrated circuits.

池保勇,清华大学 池保勇,1998年07月于北京大学获得学士学位,2003年07月于清华大学获得博士学位,毕业后留校任教至今,并曾在美国斯坦福大学进修一年,研究领域包括硅基射频/毫米波集成电路、模拟集成电路和无线通信/雷达系统芯片。目前担任清华大学集成电路学院长聘教授,副院长,某主题组副首席。先后入选国家自然科学基金委优青、教育部长江学者青年学者、教育部高层次人才计划等。发表学术论文200多篇,授权中国和美国发明专利各30多项和5项。曾经担任 IEEE TCAS-II 客座编辑、IEEE A-SSCC TPC 成员和TPC共同主席、中国科学信息科学编委和Microelectronics Journal副主编。目前担任国家重点研发计划项目“硅基超高速无线通信收发机芯片”首席科学家和某重点项目负责人。研制的毫米波雷达芯片及系统获IEEE A-SSCC SDC杰出设计奖,曾经获得霍英东教育基金、清华大学学术新人奖、产学研合作创新奖、中国电子学会优秀科技工作者等奖励。

Hybrid DC-DC Converter Design: From Seeds to Leaves

With the surging demands for extremely high current at sub-1 V supply voltage level in high performance computing, high density power delivery becomes one of the main bottlenecks for system integration. For the high current applications, high-voltage rails are essential to reduce the IR losses on the power delivery networks. Thus, there is a wide voltage gap between the power bus and the digital supply rails at the point-of-load (PoL), calling for novel power conversion topologies and system architectures. To bridge this gap, switched-capacitor-inductor (SCI) hybrid DC-DC converter has been the hottest topic in the power management IC area in the past 10 years or so. In this talk, we will review the SCI hybrid DC-DC converter from the topology “seeds” to their “leaves”, and will also introduce a few hybrid DC-DC design examples from our research group. Then, we will share several of our observations and design suggestions for future works.

路延,澳门大学 路延,博士生导师,澳门大学微电子研究院副教授,兼任深圳福田澳大河套集成电路研究院常务副院长、珠海澳大科技研究院微电子研发中心主任。2013年博士毕业于香港科技大学。2014年加入澳门大学模拟与混合信号超大规模集成电路国家重点实验室工作至今。主要研究方向包括电源管理芯片设计、无线能量传输电路与系统等。发表IC设计领域顶尖论文ISSCC+JSSC共45篇。撰写专著两本。申请十余项中美专利。曾获ISSCC 2017菅野卓雄远东最佳论文奖、IEEE电路与系统学会2017杰出青年作者奖、2021年度国家自然科学基金优青(港澳)项目。曾任IEEE JSSC、TCAS-I和TCAS-II客座编辑、IEEE SSCS杰出讲师。现任ISSCC技术委员会委员、CICC电源分会主席、《半导体学报》副主编。

Conference Committee

Conference Co-Chairs

Zhiliang Hong, Fudan University     

Yan Lu, University of Macau     

Qiang Li, University of Electronic Science and Technology of China     

Technical Program Co-Chairs

Jiawei Xu, Fudan University      

Chixiao Chen, Fudan University     

Nan Sun, Tsinghua University     

Pui-In Mak, University of Macau      

Yongpan Liu, Tsinghua University     

Dixian Zhao, Southeast University     

Conference Program

ICAC 2024 Conference Program Day0-March 19
10:00-21:00 Onsite Sign-in & Conference Bag Collection
Venue: Lobby @ Pullman Shanghai South

ICAC 2024 Conference Program Day1-March 20
8:45-10:15 Tutorial#1
Multimodal Analog Front-End Circuits for Wearable Healthcare

Reconfigurable Machine Learning Processor: Fundamental Concepts, Applications, and Future Trends
10:30-12:00 Tutorial#3
Silicon-based Millimeter Wave Integrated Circuit Design Technology
Hybrid DC-DC Converter Design: From Seeds to Leaves
14:00-14:10 开幕致辞 & ICAC 2023 Best Speaker颁奖
14:10-14:50 大会报告:刘明,复旦大学
14:50-15:30 大会报告:洪伟,东南大学
15:45-16:00 ISSCC Trends Talk#1: 罗文基,澳门大学
16:00-16:15 ISSCC Trends Talk#2: 徐鸿涛,复旦大学
16:15-16:30 ISSCC Trends Talk#3: 杨   军,东南大学
16:30-16:45 ISSCC Trends Talk#4: 张沕琳,清华大学
16:45-17:45 Welcome Reception
18:00-21:00 Industrial and Poster Session
ICAC 2024 Conference Program Day2-March 21
  Session: RF  Techniques I
Chair: 赵涤燹
Session: CIM Techniques I
Chair: 陈迟晓
Session: Data Converter I
Chair: 沈林晓
8:30-9:00 洪志良,复旦大学
A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for Large AI Models
Ways to Cure Zero-ISSCC-Paper Syndrome: From an ADC Guy Point of View
9:00-9:30 薛泉,华南理工大学
A Wideband Mode-Switching Quad-Core VCO Using Compact Multi-Mode Magnetically Coupled LC Network
A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC
An Interleaved Pipe-SAR ADC with Shared Residue Integrating Amplifier
9:30-10:00 麦沛然,澳门大学
A 167μW BLE Receiver Using a Passive Quadrature-Front-End, a Double-Sided Double-Balanced Cascaded Mixer and a Dual-Transformer-Coupled Class-D VCO
The Development Trends, Challenges, and Research Progress of SRAM-based Computing-in-Memory AI Chip
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier
10:00-10:30 吴亮,香港中文大学(深圳)
An 8.9-to-21.9GHz Single-Core Oscillator with Reconfigurable Class-F–1 and Enhanced-Colpitts Dual-Mode Operation
Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM with 3984-kb/mm² Density in 65-nm CMOS
Key Technology Research and Industrialization of Fully Digitized ADC
  Session: Wireline Techniques
Chair: 王成
Session: Sensor Interfaces
Chair: 谭志超
Session: Power Converter I
Chair: 路延
10:45-11:15 潘权,南方科技大学
A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS
A 0.028mm² 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccuracy from −40°C to 125°C and ±1600ppm Inaccuracy After Accelerated Aging
A 93.4% Peak Efficiency CLOAD-Free Multi-Phase Switched-Capacitor DC–DC Converter Achieving a Fast DVS up to 222.5 mV/ns
11:15-11:45 杜源,南京大学
Wireline Transceiver Design with Crosstalk Cancellation Techniques
A 14b BW/Power Scalable Sensor Interface with a Dynamic Bandgap Reference and an Untrimmed Gain Error of ±0.26% from -40°C to 125°C
A 200MHz-Bandwidth Envelope-Tracking Supply Modulator Using a Class-G Linear Amplifier and a Single-Inductor Dual-Input-Dual-Output Converter for 5G New Radio RF Applications
11:45-12:15 周波,北京理工大学
Low-Power Low-Complexity FM-UWB Transceiver with Digital Reuse and Analog Stacking
Sub- μ W Auto-Calibration Bandgap Voltage Reference With 1 σ Inaccuracy of ± 0.12%Within − 40°C to 120°C
A Li-ion-Battery-Input 1-to-6V-Output Bootstrap-Free Hybrid Buck-or-Boost Converter Without RHP Zero Achieving 97.3% Peak Efficiency 6μs Recovery Time and 1.13μs/V DVS Rate
  Session: mmWave Circuits and Systems
Chair: 吴亮
Session: Optical Sensors
Chair: 潘思宁
Session: Emerging Power
Chair: 程林
13:45-14:15 余益明,电子科技大学
A 22.4~30.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving >30.2dB OTA-Tested Spatial Rejection
A Spiking Vision Chip based on SPAD Imager and Reconfigurable Spike-based Vision Processor
750mW Isolated DC-DC Converter with 54/18Mbps Full-Duplex Communication Using a Single Pair of Transformers
14:15-14:45 王成,电子科技大学
A Scalable 134-to-141GHz 16-Element CMOS 2D λ/2-Spaced Phased Array
A 256x192 Pixel 30fps Automotive Direct Time-of-Flight LiDAR SoC
A Li-Ion Battery Input Highly Integrated LED Driver With 96.8% Peak Efficiency and Dual-Color Mixing Capability
14:45-15:15 贾海昆,清华大学
A Fully Integrated Bit-to-Bit Terahertz Transceive for Short Range Wireless Communications
Solid-state LiDAR for Intelligent Vehicles
A Differential Hybrid Class-ED Power Amplifier with 27W Maximum Power and 82% Peak E2E Efficiency for Wireless Fast Charging To-Go
15:15-15:45 樊超,西安交通大学
A 0.07mm² 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10MHz and 200.7dBc/Hz FoMA in 65nm CMOS
Illuminating Neural Pathways: Power-Efficient Light Time-of-Flight ICs for Non-Invasive Functional Brain Imaging
A 6.78-MHz 79.5%-Peak-Efficiency Wireless Power Transfer System using a Wireless Mode-Recognition Technique and a Fully-On/off Class-D Power Amplifier
  Session: RF Techniques II
Chair: 贾海昆
Session: Efficient Digital Circuits
Chair: 李学清
Session: SC DC-DC
Chair: 黄沫
16:00-16:30 钱慧珍,西安电子科技大学
CMOS Watt-Level Wideband 4096QAM Digital Power Amplifier Design With 45% Drain Efficiency and 115dB Dynamic Range
A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems
SC Sigma Converter for LiDAR Driver
16:30-17:00 高昊,东南大学
A 76-81 GHz 2X8 MIMO Radar Transceiver with Broadband Fast Chirp Generation and 10-Antenna-in-Package Array
Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS
Ratio-Regulatable Switched-Capacitor Converter Techniques for High-Density Point-of-Load Power Supplies
17:00-17:30 唐凯,湖南大学
A 107 pJ/b TX 260 pJ/b RX Ultra-Low-Power MEMS-based Transceiver with Wake-up in ISM-bands for IoT Applications
C3MLS: An Ultra-Wide-Range Energy-Efficient Level Shifter With CCLS/CMLS Hybrid Structure
Battery-Input Buck–Boost Hybrid DC–DC Converters
17:30-18:00 张川,东南大学
BayesBB: A 9.6Gbps 1.61ms Configurable All-Message-Passing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS
A SIDO/DISO Continuously Scalable-Conversion-Ratio SC Converter
ICAC 2024 Conference Program Day3-March 22
  Session: RF Transceivers
Chair: 邓伟
Session: CIM Techniques II
Chair: 孙亚男
Session: Data Converter II
Chair: 江文宁
8:30-9:00 殷韵,复旦大学
Design of fully-integrated multi-mode multi-band digital transmitter
A 4.8GS/s TI-SAR with Timing-Skew and Ping-Pong Comparator Offset Calibration
9:00-9:30 许灏,复旦大学
A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression
Emerging non-volatile and non-volatile/volatile Fused Computing-in-memory Macros for Edge Inference and Learning
When Time Interleaving Encounters Oversampling
9:30-10:00 孟淼,同济大学
Long Range and High Perfomance Backscatter Communication Techniques for Cattery-less IoT Systems
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM
Pursuing Better Amplifiers and Their Applications in ADCs
10:00-10:30 李巍,复旦大学
A Wideband Full-Duplex Receiver with Multi-Domain Self-interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers
A 22nm 64kb Lightning-like Hybrid Computing-in-Memory Macro with Compressed Adder tree and Analog-storage Quantizers for Transformer and CNNs
Nested Sigma-Delta Modulator Structure: A System-Level Power-Efficient Approach to Achieving High Resolution
  Session: RF Techniques III
Chair: 许灝
Session: VCOs & PLLs
Chair: 钱慧珍
Session: PMIC Techniques
Chair: 高源
10:45-11:15 邓伟,清华大学
A 6-to-11 GHz 1T2R IEEE 802.15.4/4z-Compliant Joint-Radar-Communication Transceiver SoC
Ultra-low-jitter Millimeter-Wave Fractional-N CPPLL Frequency Synthesizer Techniques
A Modified KY Converter
11:15-11:45 吕关胜,清华大学
A 4.9–7.1-GHz High-Effciency Post-Matching GaN Front-End Module for Wi-Fi 7 Application
Low-Jitter and Low-Spur Ping-Pong Sampling PLL Based on Ring Oscillator Targeting Wireline Links
A Wireless Power Transfer System with Up-to-27.9% Efficiency Improvement under Coupling Coefficient Ranging from 0.1 to 0.39 Based on Phase-Shift/Time-Constant Detection and Hybrid Transmission Power Control
11:45-12:15 李显博,中山大学
Dual-Photodiode Differential Receivers Achieving Double Photodetection Area for Gigabit-per-Second  Optical Wireless Communication
A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter and 0.55μs Locking Time
Piezoelectric Energy Harvesting Interface Using Self-bias-flip Rectifier and Switched-PEH DC-DC for MPPT
  Session: mmWave Circuits and Systems  II
Chair: 殷韵
Session: Low Power SoC
Chair: 涂锋斌
Session: Analog Techniques I
Chair: 徐佳伟
13:45-14:15 胡三明,东南大学
A 12.4% Efficiency, 11dBm Psat, Odd-Harmonics-Recycling, 62-to-92GHz CMOS Frequency Quadrupler Using an Amplitude-Phase Coordinating Technique
A High Accuracy and Energy-Efficient Zero-Shot-Retraining Seizure Detection Processor with Hybrid-Feature-Driven Adaptive Processing and Learning-Based Adaptive Channel Selection
Wireless Sensing Chips-- From 'Low Power' to 'Battery Free'
14:15-14:45 丰光银,华南理工大学
A 52–73-GHz LNA With Tri-Coupled Transformer for Gm Boosting and Enhanced Noise Canceling
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing
14:45-15:15 孙厚军,北京理工大学
High Performance Fully Integrated Silicon-based W-Band Phased-Array Transceiver Front-end
Sensors in Thermal Principle with CMOS-MEMS Technology
15:15-15:45 张雷,清华大学
A 67.8-to-108.2GHz Power Amplifier with Three-Coupled-Line-Based Complementary-Gain-Boosting Technique Achieving 443GHz GBW and 23.1% peak PAE
A Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing
High Resolution Hybrid Light-to-Digital Converter for PPG/NIRS
  Session: RF Techniques IV
Chair: 殷俊
Session: Analog Techniques II
Chair: 赵博
Session: High-Density Power Circuits
Chair: 郭建平
16:00-16:30 王勇,电子科技大学
An SP10T Switch with Reconfigurable Matching and Symmetrical Routing Topologies Functioning from DC to 18GHz
A 0.5V 6.14µW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120µs] XO Startup and [8.1nJ, 200µs] Successive-Approximation-Based RTC Calibration
A NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up to Sub 10-μs Short-Period Load Transient
16:30-17:00 李连鸣,东南大学
A 11GHz DPD FMCW PLL with 0.051% RMS Error under 2.3GHz Chirp Bandwidth, 2.3GHz/μs Slope and 50ns idle time in 65-nm CMOS
A Cryo-CMOS Quantum Computing Unit Interface Chipset in 28nm Bulk CMOS with Phase-Detection based Readout and Phase-Shifter based Pulse Generation
A Fully Synthesizable All-Digital Dual-Loop Distributed Low-Dropout Regulator
17:00-17:30 / 徐佳伟,复旦大学
A Power-Efficient Class-D Audio Amplifier with Capacitive Feedforward and PWM-Aliasing Reduction
A Flyweight 5V-to-150V Input-Parallel Output-Series Hybrid DC-DC Boost Converter
17:30-17:40 闭幕 & 2024 Best Student Poster 颁奖

Student Poster Session

In order to further encourage exchanges among students in the field of chip design, ICAC 2024 will set up a student poster session in addition to the invited talks. Students who are interested are welcome to attend and display. The best student poster award will be selected and presented at the conference. Students who participate in the poster session will receive an excellent participation experience.

The Link to submit your posters:

Important Dates:
Student Poster Submission Deadline:
31st January, 2024 8th February, 2024

Camera Ready Submission Deadline:
10th March, 2024
Student Poster Session Date:
20th March, 2024
Download the CFP Flyer

Poster List

March 20, 2024 | 18:00-21:00

icac2024posterlist1 icac2024posterlist2 icac2024posterlist3 icac2024posterlist4 icac2024posterlist5 icac2024posterlist6


Early-bird Registration Fee

(On or before Mar. 5, 2024)
  • Student: 1200 RMB
  • Regular: 2400 RMB
  • Invited Speaker: 2400 RMB

Regular Registration Fee

(After Mar. 5, 2024)
  • Student: 1500 RMB
  • Regular: 2900 RMB
  • Invited Speaker: 2400 RMB

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    1200 RMB per double tutorials
  • Regular: 1200 RMB per tutorial
    1600 RMB per double tutorials

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    For query, please contact conference secretary:

    Ms. Joyce Zhong


    Tel/Phone: (86)18628263876