Multimodal Analog Front-End Circuits for Wearable Healthcare
Simultaneous recordings of multiple physiological signals in a wearable form factor enables more easy and comprehensive assessment of one’s health condition. However, detecting low-amplitude, low-frequency physiological signals from multiple aggressors like noise, motion artifacts, and environmental interferences remains the great challenge in practice. This talk presents several recent examples of biopotential, bioimpedance and optical interface circuits, with focus on analog circuits techniques to optimize noise, input impedance, input dynamic range, and power consumption for wearable scenarios.
徐佳伟，复旦大学 Jiawei Xu received the M.Sc. and Ph.D. degrees in the Delft University of Technology, The Netherlands. From 2006 to 2018, he was with imec/Holst Centre, Eindhoven. In 2018, he joined Fudan University, Shanghai, China, as a faculty member. His research group works on integrated circuits for wearable and implantable medical devices, precision sensor interfaces, and battery power management. He is a TPC member of ISSCC and CICC, an Associate Editor for IEEE Transactions on VLSI Systems.
Reconfigurable Machine Learning Processor: Fundamental Concepts, Applications, and Future Trends
A reconfigurable ML processor increases hardware flexibility to accommodate various ML algorithms and speeds up processing time while consuming less power. Typically, a reconfigurable ML processor includes multiple reconfiguration hierarchies, such as chip-level, processing element array-level, and processing element-level reconfigurations. Chip-level reconfiguration dynamically adjusts the parallelism of multi-chip systems to minimize computation latency and data access. Processing element array-level reconfiguration changes the dataflow or mapping of the computing engine to fully reuse the on-chip data, reducing the memory access. Processing element-level reconfiguration changes the function of the computing unit, such as computing precision and sparsity processing pattern, to increase the bit-wise hardware utilization. This tutorial explores the fundamental concepts of reconfigurable technology, discusses its applications in both digital and analog ML processors, and prospects for future development trends in reconfigurable technology.
尹首一，清华大学 Shouyi Yin received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tsinghua University, Beijing, China, in 2000, 2002, and 2005, respectively. He has worked with Imperial College, London, U.K., as a Research Associate. He is currently a full professor and the vice director of School of Integrated Circuits in Tsinghua University. His research interests include reconfigurable computing, AI processors and high level synthesis. He has published more than 100 journal papers and more than 50 conference papers. He has served as technical program committee member in the top VLSI and EDA conferences such as A-SSCC, MICRO, DAC, ICCAD and ASPDAC. He is the associate editor of IEEE TCAS-I, ACM TRETS and Integration, the VLSI journal.
This tutorial mainly focused on the design technology of silicon-based millimeter-wave integrated circuits, which including the characteristics of commonly used passive components in silicon-based millimeter-wave integrated circuits (such as transmission lines, transformers), the design process of silicon-based millimeter-wave integrated circuits, the design methods of core circuit modules (such as low-noise amplifiers, power amplifiers, voltage-controlled oscillators), and considerations for system-level link design. This tutorial integrated the research progress of the research group, aiming to help the audience to understand the basic design methods and the latest developments in the field of silicon-based millimeter-wave integrated circuits.
Hybrid DC-DC Converter Design: From Seeds to Leaves
With the surging demands for extremely high current at sub-1 V supply voltage level in high performance computing, high density power delivery becomes one of the main bottlenecks for system integration. For the high current applications, high-voltage rails are essential to reduce the IR losses on the power delivery networks. Thus, there is a wide voltage gap between the power bus and the digital supply rails at the point-of-load (PoL), calling for novel power conversion topologies and system architectures. To bridge this gap, switched-capacitor-inductor (SCI) hybrid DC-DC converter has been the hottest topic in the power management IC area in the past 10 years or so. In this talk, we will review the SCI hybrid DC-DC converter from the topology “seeds” to their “leaves”, and will also introduce a few hybrid DC-DC design examples from our research group. Then, we will share several of our observations and design suggestions for future works.