Design Your Low Power Delta-Sigma ADC: From 0 to 1
Delta-Sigma ADCs are the most widely used solutions to high-precision conversion applications. This tutorial provides a comprehensive overview of delta-sigma ADCs with basic principles and design examples. We start with the concepts of oversampling and noise shaping. We cover various behavioral topologies and circuit implementations of delta-sigma ADCs, revealing the trade-offs and design considerations for higher energy efficiency. Recent advances in low-power delta-sigma ADCs will also be provided. This tutorial provides intuitive explanations and design insights, aiming to help the beginners have a solid understanding and quickly get started with designing their own delta-sigma ADCs.
谭志超,浙江大学 Zhichao Tan (Senior Member, IEEE) received the B.Eng. degree from Xi’an Jiaotong University, Xi’an, China, in 2004, the M.Eng. degree from Peking University, Beijing, China, in 2008, and the Ph.D. degree from Delft University of Technology, Delft, The Netherlands, in 2013. He was a Staff IC Design Engineer working on low-power, high-precision analog/mixed-signal circuit design with Analog Devices Inc., Wilmington, MA, USA, from 2013 to 2019. He joined Zhejiang University, Hangzhou, China, as a Faculty Member in 2019. His research interests include energy-efficient sensor interfaces, precision analog circuits, and ultra-low-power analog-to-digital converters (ADCs). This has resulted in over 85 technical journal and conference papers. He holds five U.S. patents.Dr. Tan is a TPC member of the IEEE Custom Integrated Circuits Conference. He was a TPC member of the IEEE Asian Solid-State Circuits Conference. He has served as Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, IEEE Sensors Journal, and IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS.
2.5D/3D/3.5D Integration: Fabrication and Chiplet Partition
High-performance, low-phase-noise oscillators are heavily demanded by high-throughput and high-fidelity mm-wave transceivers. The content of this tutorial includes: (1) the oscillator’s performance matrix and key Figure of Merit (FoM); (2) the reactive-load design, namely - inductors/transformers and tunable capacitors, for achieving high quality factor and the design challenge for mm-wave oscillators; (3) various oscillator topologies to reduce phase noise at the mm-wave frequency, such as Class-C and harmonic shaping; (4) the design of multi-core synchronized oscillator, which provides an opportunity for further reducing phase noise; (5) frequency tuning range extension for multi-core oscillators with the aid of mode-switching and multi-resonance techniques.
High-Performance PLLs: Evolution, Challenges, and Future Directions
Phase-locked loop (PLL) is one of the key techniques for both communication and radar systems. Various functions in communication and radar systems, including clock generation, frequency synthesis, serial-to-parallel conversion, frequency and phase modulation, clock synchronization and distribution, coherent and non-coherent demodulation, clock and carrier recovery, directly or indirectly rely on PLLs. High performance PLL is one of the cutting-edge topics in the field of integrated circuit and system design. It involves various research directions such as mixed-signal circuit design, digital algorithms, and system-level architecture. This lecture will discuss the high-performance PLL circuit and architecture evolution, review the latest research progress and discuss the future development trends of high-performance PLLs.